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TDA9110
LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PRODUCT PREVIEW
I C GEOMETRY CORRECTIONS VERTICAL PARABOLA GENERATOR (Pincushion, Keystone) HORIZONTAL SIZE CONTROL (Amplitude) HORIZONTAL DYNAMIC PHASE (Side Pin Balance & Parallelogram) HORIZONTAL AND VERTICAL DYNAMIC FOCUS (Horizontal Focus Amplitude, Horizontal Focus Symmetry, Vertical Focus Amplitude) GENERAL SYNCHRO PROCESSOR 12V SUPPLY VOLTAGE 8V REFERENCE VOLTAGE HOR. & VERT. LOCK UNLOCK OUTPUTS READ/WRITE I 2C INTERFACE HORIZONTAL AND VERTICAL MOIRE DESCRIPTION The TDA9110 is a monolithic integrated circuit assembled in 32-pin shrunk dual in line plastic package. This IC controls all the functions related to the horizontal and vertical deflection in multimode or multi-frequency computer display monitors. The internal synchro processor, combined with the very powerful geometry correction block make the TDA9110 suitable for very high performance monitors with very few external components. The horizontal jitter level is extremely low. (Typical standard deviation : 300ps @ 31kHz). It is particularly well suited for high-end 15" and 17" monitors.
December 1997
. . . . . . . . . . . . . . . . . . . . .
2
HORIZONTAL EXTREMELY LOW JITTER LEVEL SELF-ADAPTATIVE DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY X-RAY PROTECTION INPUT I2C CONTROLS : HORIZONTAL DUTY-CYCLE, H-POSITION VERTICAL VERTICAL RAMP GENERATOR 50 TO 165Hz AGC LOOP GEOMETRY TRACKING WITH V-POS & AMP I2C CONTROLS : V-AMP, V-POS, S-CORR, C-CORR DC BREATHING COMPENSATION
Combined with ST7275 Microcontroller family, TDA9206 (Video preamplifier) and STV942x (On-Screen Display controller) the TDA9110 allows to built fully I2C bus controlled computer display monitors, with a reduce nu mber of external compon ents.
SHRINK32 (Plastic Package) ORDER CODE : TDA9110
PIN CONNECTIONS
H/HVIN VSYNC-IN HMOIRE HLOCKOUT PLL2C FC1 C0 R0 PLL1F HPOS HGND HFLY HREF HLOCKCAP HVFOCUS HFOCUSCAP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5V SDA SCL VCC HSIZE GND HOUT XRAY EWOUT VOUT VCAP VREF VAGCCAP VGND DCBREATH GND
9110-01.EPS
1/29
This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice.
TDA9110
PIN CONNECTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name H/HVIN VSYNCIN HMOIRE HLOCKOUT PLL2C FC1 C0 R0 PLL1F HPOS HGND HFLY HREF HLOCKCAP FOCUSOUT HFOCUSCAP GND BREATH VGND VAGCCAP VREF VCAP VOUT EWOUT XRAY HOUT GND HSIZE VCC SCL SDA 5V Function TTL compatible Horizontal Synchro Input TTL compatible Vertical Synchro Input (for separated H&V) Horizontal Moire Output (to be connected to PLL2C through a resistor divider) First PLL Lock/Unlock Output (0V unlocked - 5V locked) Second PLL Loop Filter High Threshold VCO Decoupling Filter Horizontal Oscillator Capacitor Horizontal Oscillator Resistor First PLL Loop Filter Horizontal Position Decoupling Filter Horizontal Section Ground Horizontal Flyback Input (positive polarity) Horizontal Section Reference Voltage (to be filtered) First PLL Lock/Unlock Time Constant Capacitor Mixed Horizontal and Vertical Dynamic Focus Output Horizontal Dynamic Focus Oscillator Capacitor Ground (related internal reference) DC Breathing Input Control Vertical Section Ground Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator Vertical Section Reference Voltage (to be filtered) Vertical Sawtooth Generator Capacitor Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if any). It is mixed with vertical position reference voltage output and vertical moire. East/West Pincushion Correction Parabola Output X-RAY protection input (with internal latch function) Horizontal Drive Output (int. trans. open collector) General Ground (referenced to VCC) DC HSize Control Output Supply Voltage (12V Typ) I2C Clock Input I2C Data Input Supply Voltage (5V Typ.)
9110-01.TBL
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TDA9110
QUICK REFERENCE DATA
Parameter Horizontal Frequency Autosynch Frequency (for given R0 and C0) Horizontal Synchro Polarity Input Polarity Detection (on both Horizontal and Vertical Sections) TTL Composite Synchro Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) I C Control for H-Position XRay Protection I2C Horizontal Duty Adjust I C Free Running Adjustment Stand-by Function Two Polarities H-Drive Outputs Supply Voltage Monitoring PLL1 Inhibition Possibility Horizontal Blanking Output Vertical Frequency Vertical Autosync (for 150nF) Vertical S-Correction Vertical C-Correction Vertical Amplitude Adjustment DC Breathing Control on Vertical Amplitude Vertical Position Adjustment East/West Parabola Output Pin Cushion Correction Amplitude Adjustment Keystone Adjustment Internal Dynamic Horizontal Phase Control Side Pin Balance Amplitude Adjustment Parallelogram Adjustment Tracking of Geometric Corrections Reference Voltage (both on Horizontal and Vertical) Dynamic Focus (both Horizontal and Vertical) I C Horizontal Dynamic Focus Amplitude Adjustment I2C Horizontal Dynamic Focus Keystone Adjustment I C Vertical Dynamic Focus Amplitude Adjustment Type of Input Synchro Detection (supplied by 5V Digital Supply) Vertical Moire Output I2C Controlled V-Moire Amplitude Frequency Generator for Burn-in Fast I C Read/Write Horizontal Moire Output I C controlled H-Moire Amplitude DC HSize Output Amplitude Control
2 2 2 2 2 2
Value 15 to 150 1 to 4.5 F0 YES YES YES YES 10 YES 30 to 60 NO YES NO YES NO YES 35 to 200 50 to 150 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES NO 400 YES YES YES
Unit kHz
% %
Hz Hz
kHz
9110-02.TBL
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PLL1F
HPOS
HLOCKOUT
HLOCKCAP
R0
C0
FC1
HFLY
PLL2C
BLOCK DIAGRAM
9 10
4
14
8
7
6
12
5
26
HREF 13
VREF
HGND 11 VCO PHASE COMPARATOR PHASE SHIFTER H-DUTY (5 bits) HOUT BUFFER
VREF 21
VREF
PHASE/FREQUENCY COMPARATOR H-PHASE (7 bits)
VGND 19 LOCK/UNLOCK IDENTIFICATION X2 Spin Bal 6 bits X
2
H/HVIN
1
VSYNCIN
2
SYNC INPUT SELECT (1 bit)
SYNC PROCESSOR
SAFETY PROCESSOR
VCC XRAY 16 HFOCUSCAP
5 bits Key Bal 6 bits GEOMETRY TRACKING 6 bits 6 bits VMOIRE 5 bits VPOS 7 bits VAMP 7 bits
HMOIRE
3
HFLY VSYNC
Amp (7bits) Kest (5 bits)
HSIZE 28
7 bits
X2 PCC 7 bits X2 VFOCUS 6 bits
HOUT
VCAP
VAGCCAP
VOUT
9110-02.EPS
DCBREATH
EWOUT
4/29
X2 15 HVFOCUS 29 VCC 17 GND S AND C CORRECTION VERTICAL OSCILLATOR RAMP GENERATOR Keyst. 6 bits X 25 XRAY 22 20
TDA9110
5V 32
RESET GENERATOR
SDA 31
SCL 30
I2C INTERFACE
GND 27 18 23 24
TDA9110
TDA9110
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDD VIN Parameter Supply Voltage (Pin 29) Supply Voltage (Pin 32) Max Voltage on Pin 12 Pin 5 Pin 16 Pin 7 Pins 8, 9, 14, 20, 22 Pin 15, 18, 23, 24, 25, 26, 28 Pins 1, 2, 3, 4, 30, 31 ESD susceptibility Human Body Model,100pF Discharge through 1.5k EIAJ Norm,200pF Discharge through 0 Max. Sourced Current (Pin 28) Max. Sunk Current (Pin 28) Storage Temperature Junction Temperature Operating Temperature Value 13.5 5.7 1.8 4.0 5.5 6.4 8.0 VCC VDD 2 300 2.5 100 -40, +150 +150 0, +70 Unit V V V V V V V V V kV V mA A o C o C o C
VESD HSize Cur Tstg Tj Toper
THERMAL DATA
Symbol Rth (j-a) Parameter Junction-ambient Thermal Resistance Max. Value 65 Unit
o
C/W
SYNCHRO PROCESSOR Operating Conditions (VDD = 5V, T amb = 25oC)
Symbol HsVR MinD Mduty VsVR VSW VSmD VextM Parameter Horizontal Synchro Input Voltage Minimum Horizontal Input Pulses Duration Maximum Horizontal Input Signal Duty Cycle Vertical Synchro Input Voltage Minimum Vertical Synchro Pulse Width Maximum Vertical Synchro Input Duty Cycle Maximum Vertical Synchro Width on TTL H/Vcomposite Test Conditions Pin 1 Pin 1 Pin 1 Pin 2 Pin 2 Pin 2 Pin 1 Min. 0 0.7 0 5 Typ. Max. 5 25 5 15 750 Unit V s % V s % s
Electrical Characteristics (VDD = 5V, Tamb = 25oC)
Symbol VINTH RIN VOut TfrOut VHlock VoutT Parameter Horizontal and Vertical Input Threshold Voltage (Pins 1, 2) Horizontal and Vertical Pull-Up Resistor Output Voltage (Pin 4) Falling and Rising Output CMOS Buffer Horizontal 1st PLL Lock Output Status (Pin 4) Extracted Vsync Integration Time (% of TH) on H/V Composite Test Conditions Low Level High Level Pins 1, 2 Low level High Level Pin 4, Cout = 20pF Locked Unlocked C0 = 820pF Min. 2.2 200 0 5 200 0 5 35 Typ. Max. 0.8 Unit V V k V V ns V V %
26
I2C READ/WRITE Electrical Characteristics (VDD = 5V,Tamb = 25oC)
Symbol I C PROCESSOR Fscl Tlow Thigh Vinth VACK
2
Parameter Maximum Clock Frequency Low period of the SCL Clock High period of the SCL Clock SDA and SCL Input Threshold Acknowledge Output Voltage on SDA input with 3mA
Test Conditions Pin 30 Pin 30 Pin 30 Pins 30,31 Pin 31
Min.
Typ.
Max. 400
Unit kHz s s V V 5/29
2
2.2 0.4
See also I C Table Control and I2C Sub Address Control
9110-05.TBL
1.3 0.6
9110-04.TBL
9110-03.TBL
TDA9110
HORIZONTAL SECTION Operating Conditions
Symbol VCO R0(Min.) C0(Min.) F(Max.) Minimum Oscillator Resistor Minimum Oscillator Capacitor Maximum Oscillator Frequency Pin 8 Pin 7 4 390 150 k pF kHz Parameter Test Conditions Min. Typ. Max. Unit
OUTPUT SECTION I12m HOI Maximum Input Peak Current Horizontal Drive Output Maximum Current Pin 12 Pin 26, Sunk current 2 30 mA mA
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Symbol Parameter Test Conditions Min. Typ. Max. Unit SUPPLY AND REFERENCE VOLTAGES VCC VDD ICC IDD VREF-H VREF-V IREF-H IREF-V Supply Voltage Supply Voltage Supply Current Supply Current Horizontal Reference Voltage Vertical Reference Voltage Max. Sourced Current on VREF-H Max. Sourced Current on VREF-V Pin 29 Pin 32 Pin 29 Pin 32 Pin 13, I = 5mA Pin 21, I = 5mA Pin 13 Pin 21 7.4 7.4 10.8 4.5 12 5 50 5 8 8 8.6 8.6 5 5 13.2 5.5 V V mA mA V V mA mA
1st PLL SECTION HpolT VVCO Polarity Integration Delay VCO Control Voltage (Pin9) VREF-H = 8V f0 fH(Max.) R0 = 5.9k, C0 = 820pF, dF/dV = 1/11R0 C0 % of Horizontal Period Sub-Address 01 Byte x1111111 Byte x1000000 Byte x0000000 R0 = 5.9k, C0 = 820pF, f0 = 0.97/8R0C 0 See Note R0 = 6.49k, C0 = 820pF, from f0+0.5kHz to 4.5F0 fH(Min.) fH(Max.) Component accuracy : C0 = 2%, R0 = 1% 0.75 VREF-H / 6 6.2 18.8 10 2.6 3.2 3.8 25 -150 ms V V kHz % V V V kHz ppm/C
Vcog Hph Hphmin Hphtyp Hphmax f0 dF0/dT CR
VCO Gain (Pin 9) Horizontal Phase Adjustment Horizontal Phase Setting Value Minimum Value Typical Value Maximum Value Free Running Frequency Free Running Frequency Thermal Drift (No drift on external components) PLL1 Capture Range
100
Note : This parameter is not tested on each unit. It is measured during our internal qualification.
6/29
9110-05.TBL
28
kHz kHz
TDA9110
HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit 2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION FBth Hjit Flyback Input Threshold Voltage (Pin 12) Horizontal Jitter Horizontal Drive Output Duty-Cycle (Pin 26) (see Notes 1 & 2) Low Level High Level X-RAY Protection Input Threshold Voltage Horizontal Freq. = 31kHz Sub-Address 00 Byte xxx11111 Byte xxx00000 Pin 25 30 60 8 1.6 3.7 7.5 0.4 % % V V V V V 0.65 0.75 60 V ppm
HDmin HDmax XRAYth Vphi2 VSCinh HDvd
Internal Clamping Levels on 2nd PLL Loop Low Level Filter (Pin 5) High Level Threshold Voltage To Stop H-Out,V-Out when VCC < VSCinh Horizontal Drive Output (low level) Pin 29 Pin 26 IOUT = 30mA
HORIZONTAL DYNAMIC FOCUS FUNCTION HDFst Horizontal Dynamic Focus Sawtooth Minimum Level Maximum Level Horizontal Dynamic Focus Sawtooth Discharge Width Internal fixed Phase Advance versus Hfly Middle Bottom DC Output Level DC Output Voltage Thermal Drift Horizontal Dynamic Focus Amplitude Min Byte x1111111 Typ Byte x1000000 Max Byte x0000000 Sub-Address 03, Pin 15, FH = 50kHz, Keystone Typ HfocusCap = C0 = 820pF, TH=TBD, Pin 16 Start by HDFstart Fixed for each frequency (Pin 16) RLOAD = 10k, Pin 15 2 4.7 400 860 2 200 1.1 1.7 3.5 V V ns ns V ppm/C VPP VPP VPP
HDFdis HDFstart HDFDC TDHDF HDFamp
HDFKeyst Horizontal Dynamic Focus Keystone Min A/B Byte xxx11111 Typ Byte xxx10000 Max A/B Byte xxx00000
Sub-Address 04, FH = 50kHz, Typ Amp B/A A/B A/B
2.5 1.0 2.5
VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola) AMPVDF Vertical Dynamic Focus Parabola (added to horizontal one) Amplitude with VOUT and VPOS Typical Min. Byte 000000 Typ. Byte 100000 Max. Byte 111111 Sub-Address 0F 0 0.5 1 0.6 1 1.5 0.52 0.52 VPP VPP VPP VPP VPP VPP
9110-05.TBL
VDFAMP
Parabola Amplitude Function of VAMP Sub-Address 05 (tracking between VAMP and VDF) with Byte 10000000 VPOS Typ. Byte 11000000 (see Figure 1 and Note 3) Byte 11111111
VHDFKeyt Parabola Assymetry Function of VPOS Sub-Address 06 Control (tracking between VPOS and VDF) Byte x0000000 with VAMP Max. Byte x1111111
Notes : 1. Duty Cycle is the ratio of power transistor OFF time period. Power transistor is OFF when output transistor is OFF. 2. Initial Condition for Safe Operation Start Up 3. S and C correction are inhibited so the output sawtooth has a linear shape.
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TDA9110
VERTICAL SECTION Operating Conditions
Symbol OUTPUTS SECTION VEWM VEWm RLOAD Maximum EW Output Voltage Minimum EW Output Voltage Minimum Load for less than 1% Vertical Amplitude Drift Pin 24 Pin 24 Pin 20 6.5 1.8 65 V V M Parameter Test Conditions Min. Typ. Max. Unit
Electrical Characteristics (VCC = 12V, Tamb = 25oC)
Symbol VERTICAL RAMP SECTION VRB VRT VRTF VSTD VFRF ASFR RAFD Rlin Vpos Voltage at Ramp Bottom Point Voltage at Ramp Top Point (without Synchro) Vertical Sawtooth Discharge Time Duration (Pin 22) Vertical Free Running Frequency (see Notes 4 & 5) AUTO-SYNC Frequency Ramp Amplitude Drift versus Frequency at Maximum Vertical Amplitude Ramp Linearity on Pin 22 (see Notes 4 & 5) Vertical Position Adjustment Voltage (Pin23 - VOUT centering) VREF-V=8V, Pin 22 Pin 22 With 150nF Cap COSC (Pin 22) = 150nF Measured on Pin22 C22 = 150nF 5% See Note 6 C22 = 150nF 50Hz < f and f < 165Hz 2.5 < V22 and V22 < 4.5V Sub Address 06 Byte x0000000 Byte x1000000 Byte x1111111 Sub Address 05 Byte x0000000 Byte x1000000 Byte x1111111 Subaddress 07 V/VPP at T/4 V/VPP at 3T/4 SubAddress 08 Byte x1000000 Byte x1100000 Byte x1111111 50 200 0.5 3.2 3.5 3.8 2.25 3 3.75 5 -4 +4 -3 0 3 3.3 2 5 VRT0.1 70 100 165 V V V s Hz Hz ppm/Hz % V V V V V V mA % % % % %
9110-05.TBL
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Voltage at Ramp Top Point (with Synchro) VREF-V Pin 22
3.65
VOR
Vertical Output Voltage (peak-to-peak on Pin 23)
2.5
3.5
VOI dVS
Vertical Output Maximum Current (Pin23) Max Vertical S-Correction Amplitude x0xxxxxx inhibits S-CORR x1111111 gives max S-CORR Vertical C-Corr Amplitude x0xxxxxx inhibits C-CORR
Ccorr
Notes : 4. With Register 07 at Byte x0xxxxxx (Vertical S-Correction Control) then the S correction is inhibited, consequently the sawtooth has a linear shape. 5. With Register 08 at Byte x0xxxxxx (Vertical C - Correction Control) then the C correction is inhibited, consequently the sawtooth has a linear shape. 6. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on Pin 22 and with a constant ramp amplitude.
8/29
TDA9110
VERTICAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol EAST/WEST FUNCTION EWDC TDEWDC EWpara DC Output Voltage with Typ Vpos,Keystone, Corner and Corner Balance Inhibited DC Output Voltage Thermal Drift Parabola Amplitude with Vamp Max, V-Pos Typ, Keystone Inhibited Pin 24, see Figure 2 See Note 7 Subaddress 0A Byte 11111111 Byte 10100000 Byte 10000000 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 09 Byte 1x000000 Byte 1x111111 Subaddress 06 2.5 100 2.5 1.25 0 0.45 0.8 1.25 0.9 0.9 V ppm/C V V V V V V VPP VPP Parameter Test Conditions Min. Typ. Max. Unit
EWtrack
KeyAdj
KeyTrack
Parabola Amplitude Function of V-AMP Control (tracking between V-AMP and E/W) with Typ Vpos, Keystone, EW Typ Amplitude (see Note 8) Keystone Adjustment Capability with Typ Vpos, EW Inhibited and Vertical Amplitude Max. (see Note 8 and Figure 4) Intrinsic Keystone Function of V-POS Control (tracking between V-POS and EW) with EW Max Amplitude and Vertical Amplitude Max. (see Note 8) A/B Ratio B/A Ratio DC HSize Output Level (Pin 28)
Byte x0000000 Byte x1111111 Subaddress 0B Byte 00000000 Byte 01000000 Byte 01111111 Subaddress 0D Byte x1111111 Byte x1000000 Subaddress 05 Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 0E Byte x1111111 Byte x1000000 Subaddress 06
0.52 0.52
DC HSIZE OUTPUT CONTROL HSize out 0.5 2.5 4.5 V V V
INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION SPBpara Side Pin Balance Parabola Amplitude (Figure 3) with Vamp Max, V-POS Typ and Parallelogram Inhibited (see Notes 8 & 9) Side Pin Balance Parabola Amplitude function of Vamp Control (tracking between Vamp and SP B) w it h SP B Ma x, V- PO S T yp and Parallelogram Inhibited (see Notes 8 & 9) Parallelogram Adjustment Capability with Vamp Max, V-POS Typ and SPB Max (see Notes 8 & 9) Intrinsic Parallelogram Function of Vpos Control (tracking between V-Pos and DHPC) with Vamp Max, SPB Max and Parallelogram Inhibited (see Notes 8 & 9) A/B Ratio B/A Ratio Vertical Moire (measured on VOUTDC) (Pin 23) +1.4 -1.4 0.5 0.9 1.4 +1.4 -1.4 %TH %TH %TH %TH %TH %TH %TH
SPBtrack
ParAdj
Partrack
Byte x0000000 Byte x1111111 Subaddress 0C Byte 01x11111 V18 > VREF-V V18 = VREF-V V18 = VREF-V - 4V
0.52 0.52
VERTICAL MOIRE VMOIRE 6 0 0 -10 mV % % %
9110-05.TBL
BREATHING COMPENSATION BRADj Vertical Output Variation versus DC Breathing Control (Pin 23)
Notes : 7. These parameters are not tested on each unit. They are measured during our internal qualification 8. Refers to Notes 4 & 5 from last section. 9. TH is the Horizontal PLL Period Duration.
9/29
TDA9110
Figure 1 : Vertical Dynamic Focus Function Figure 2 : E/W Output
B
VDFDC A
VDFAMP
B
9110-03.EPS
EWPARA A
9110-04.EPS
EWDC
Figure 3 :
Dynamic Horizontal Phase Control Output
Figure 4 :
Keystone Effect on E/W Output (PCC Inhibited)
B A
Keyadj
9110-05.EPS
DHPCDC
10/29
9110-06.EPS
SPBPARA
TDA9110
TYPICAL VERTICAL OUTPUT WAVEFORMS
Function Sub Address Pin Byte
VOUTDC
Specification
Picture Image
2.25V
10000000 Vertical Size 05 23
VOUTDC
11111111
3.75V
Vertical Position DC Control
06
23
x0000000 x1000000 x1111111
3.2V 3.5V 3.8V
0xxxxxxx Inhibited Vertical S Linearity 07 23 1x111111
VPP V = 4% V PP V
1x000000 Vertical C Linearity 08 23
VPP
V V = 3% V PP V
1x111111
VPP V = 3% V PP
11/29
9110-06.TBL / 9110-07.EPS TO 9110-13.EPS
TDA9110
GEOMETRY OUTPUT WAVEFORMS
Function Sub Address Pin Byte EWamp Inhibited. 1X000000 Trapezoid Control 09 24 1X111111
2.5V 0.9V 2.5V
Specification
Picture Image
0.9V
Keystone Inhibited Pin Cushion Control 10000000 0A 24
2.5V 2.5V 0V
11111111
SPB Inhibited Parrallelogram Control 1x000000 0E Internal 1x111111
3.7V 1.4% TH 3.7V 1.4% TH
Parallelogram Inhibited Side Pin Balance Control 1x000000 0D Internal 1x111111
1.4% TH
1.4% TH 3.7V
Vertical Dynamic Focus with Horizontal
32
2V
12/29
9110-07.TBL / 9110-14.EPS TO 9110-22.EPS
3.7V
TDA9110
I2C BUS ADDRESS TABLE Sub Address Definition Slave Address (8C) : Write Mode
D8 0 1 2 3 4 5 6 7 8 9 A B C D E F x x x x x x x x x x x x x x x x D7 x x x x x x x x x x x x x x x x D6 x x x x x x x x x x x x x x x x D5 x x x x x x x x x x x x x x x x D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Horizontal Drive Selection / Horizontal Duty Cycle Horizontal Position Horizontal Moire Control Synchro Priority / Horizontal Focus Amplitude Refresh / Horizontal Focus Keystone Vertical Ramp Amplitude Vertical Position Adjustment S Correction C Correction E/W Keystone E/W Amplitude Horizontal Size Control Vertical Moire Side Pin Balance Parallelogram Vertical Dynamic Focus Amplitude
Slave Address (8D) : Read Mode
D8 0 x D7 x D6 x D5 x D4 0 D3 0 D2 0 D1 0 Synchro and Polarity Detection
13/29
TDA9110
I2C BUS ADDRESS TABLE (continued)
D8 WRITE MODE 00 Xray 1, reset [0] HMoire 1, on [0], off Sync 0, Comp [1], Sep Detect Refresh [0], off Vramp 0, off [1], on HDrive 0, off [1], on Horizontal Duty Cycle [0] [0] [0] [0] [0] D7 D6 D5 D4 D3 D2 D1
Horizontal Phase Adjustment [1] [0] [0] [0] [0] [0] [0]
01
Horizontal Moire Amplitude [0] [0] [0] [0] [0]
02
Horizontal Focus Amplitude [1] [0] [0] [0] [0] [0] [0]
03
Horizontal Focus Keystone [1] [0] [0] [0] [0]
04
Vertical Ramp Amplitude Adjustment [1] [1] [0] [0] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]
05 06 07
Vertical Position Adjustment S Select 1, on [0] C Select 1, on [0] EW Key 0, off [1] EW Sel 0, off [1] Test H 1, on [0], off Test V 1, on [0], off SPB Sel 0, off [1] Parallelo 0, off [1] [0] [0] S Correction [0] [0]
C Correction [1] [0] [0] [0] [0] [0]
08
East/West Keystone [1] [0] [0] East/West Amplitude [1] [1] Moire 1, on [0] [0] [0] [0] HSize Control [0] [0] [0] [0] Vertical Moire [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]
09
0A
0B
0C
Side Pin Balance [1] [0] [0] [0] [0] [0]
0D
Parallelogram [1] [1] [0] [0] [0] [0] [0] [0] [0] [0] Synchro Detection Vext det [0], no det H/V det [0], no det V det [0], no det [0] [0]
0E 0F
Vertical Dynamic Focus Amplitude
READ MODE 00 Hlock 0, on [1], no Vlock 0, on [1], no Xray 1, on [0], off Polarity Detection H/V pol V pol [1], negative [1], negative
[ ] initial value
Data are transferred with vertical sawtooth retrace.
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TDA9110
OPERATING DESCRIPTION I - GENERAL CONSIDERATIONS I.1 - Power Supply The typical values of the power supply voltages VCC and VDD are 12V and 5V respectively. Perfect operation is obtained for VCC between 10.8 and 13.2V and VDD between 4.5 and 5.5V. In order to avoid erratic operation of the circuit during transient phase of VCC switching on, or off, the value of VCC is monitored and the outputs of the circuit are inhibited if VCC is less than 7.5V typically. Similarly,VDD is monitored and internally set-up until VDD reaches 4V (see I 2C Control Table for power on reset). In order to have a verygood powersupply rejection, the circuit is internally supplied by several voltage references(typical value : 8V).Two of thesevoltage references are externally accessible, one for the vertical and one for the horizontal part. If needed, these voltage references can be used (if ILOAD is less than 5mA). It is necessary to filter the a.m. voltage references by external capacitors connected to ground, in order to minimize the noise and consequently the "jitter" on vertical and horizontal output signals. I.2 - I2C Control TDA9110 belongs to the I2C controlled device family. Instead of being controlled by DC voltages on dedicated control pins, each adjustment can be done via the I2C Interface. The I2C bus is a serial bus with a clock and a data input. Thegeneral functionand thebus protocolare specified in the Philips-bus data sheets. The interface (Data and Clock) is TTL-level compatible. The internal threshold level of the input comparator is 2.2V (when VDD is 5V). Spikes (up to 50ns) are filtered by an integrator and the clock speed is limited to 400kHz. The data line (SDA) can be used bidirectionally(i.e. in read-mode the IC clocks out a reply information (1 byte) to the micro-processor). The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to transmit the IC-address(7 bits-8C) and the read/write bit (0 write - 1 read). I.3 - Write Mode In write mode the second byte sent contains the subaddress of the selected function to adjust (or controlsto affect)and the third byte the corresponding data byte.It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automaticallyby one the momentary subaddressin the subaddress counter (auto-increment mode). So it is possible to transmit immediately the next data bytes without sending the IC address or subaddress.It can be useful to reinitialize the whole controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 16 adjustment capabilities : 2 for the Horizontal part, 4 for the Vertical, 2 for the E/W correction, 2 for the Dynamic Horizontal phase control,2 for the Moire options, 3 for the Horizontal and Vertical Dynamic Focus and 1 for the HSize amplitude control. 15 bits are also dedicated to several controls (ON/OFF, Synchro Priority, Detection Refresh and Xray reset). I.4 - Read Mode During the read mode the second byte transmits the reply information. The reply byte contains the Horizontal and Vertical Lock/Unlock status, the Xray activation status and, the Horizontaland Vertical polarity detection.It also contains the Synchro detection status which is used by the MCU to assign the Synchro priority. A stop conditionalways stops all the activities of the bus decoder and switches to high impedance both for the data and the clock line (SDA and SCL). See I2C Subaddress and control tables. I.5 - Synchro Processor TheinternalSynchroProcessor allowsthe TDA9110 to accept any kind of input synchro signals : - separated Horizontal & Vertical TTL-compatible synchro signals, - composite Horizontal &Vertical TTL-compatible synchro signals. I.6 - Synchro Identification Status The MCU can choose via the I2C the synchro priority thanks to the system identification status provided by the TDA9110. The extracted Vertical synchro pulse is available when this identification status has been received and when the 12V is supplied. Even in Power managementmode the IC is able to inform the MCU that synchrosignals were detected due to its 5V supply. We recommend to use the device as following : first, refresh the synchro detection by I2C, then check the status of H/V det and Vdet by I2C read. Sync priority choice should be :
Vext H/V det det No Yes Yes Yes V det Yes No Sync priority Subaddress 03 D8 D7 1 0 1 1 Comment Synchro type Separated H & V Composite TTL H&V 15/29
TDA9110
OPERATING DESCRIPTION (continued) Of course, when the choice is done, we can refresh the synchro detectionsand verify that the extracted Vsync is present and that no synchro type change have occured. Synchro processor is also giving synchro polarity information. I.7 - IC status TheIC can inform the MCUabout the 1st Horizontal PLL or Vertical section status (locked or not), and about the Xray protection (activated or not). Resettingthe Xray internal latch can be done either by decreasing the VCC supply or directly resetting via the I2C interface. I.8 - Synchro Inputs Both H/HVin and Vsyncin inputs are TTL compatible triggers with Hysterisis to avoid erratic detection. It includes pull up resistor to VDD. I.9 - Synchro Processor Output The synchro processor delivers the Hlockout signal on a TTL-compatible CMOS output. Hlockout is the Horizontal 1st PLL status (5V when locked). It allows the MCU to check the Horizontal IC locking. II - HORIZONTAL PART II.1 - Internal Input Conditions A digital signal (Horizontal synchro pulse or TTL composite) is sent by the synchro processor to the horizontal part. Positive or negative signal can be applied to the Horizontal part input (see Figure 6). Using internal integration, both signals are recognized if Z/T < 25%. Synchronization occurs on the leading edge of the internal synchro signal. The minimum value of Z is 0.7s. Figure 6 Figure 7
C d d
9110-24.EPS 9110-25.EPS
TRAMEXT
The last feature performed is the removing of equalizing pulses to avoid parasitic pulses on phase comparator input (which is sensitive to wrong or missing pulses). II.2 - PLL1 The PLL1 consists of a phase comparator, an external filter and a voltage control oscillator (VCO). The phase comparator is a "phase frequency" type designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a "charge pump", composed of two current sources sunk and sourced(Typically I = 1mA when locked and I = 140A when unlocked). This difference between lock/unlock permits a smooth catching of the horizontal frequency by the PLL1. This effect is reinforced by an internal original slow down system when the PLL1 is locked, avoiding the Horizontal frequency to change too fast. The dynamic behaviour of the PLL1 is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used (see Figure 8). Figure 8
PLL1F
7
An other integration is able to extract vertical pulse of composite synchro if duty cycle is higher than 25% (typically d = 35%) (see Figure 7).
ThePLL1isinternallyinhibitedduringextractedvertical synchro (if any) to avoid taking in account missing pulses or wrong pulses on phase comparator.The inhibition results from the opening of a switch located betweenthe chargepumpand thefilter (see Figure 9). The VCO uses an external RC network. It delivers a linear sawtooth obtained by the charge and the discharge of the capacitor, with a current proportionnal to the current in the resistor. The typical thresholds of the sawtooth are 1.6V and 6.4V.
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TDA9110
OPERATING DESCRIPTION (continued) Figure 9 : Principle Diagram
H-LOCKCAP
8
LOCK/UNLOCK STATUS TRAMEXT High
PLL1F
7
R0
6
C0
5
LOCKDET
HSYNC
INPUT INTERFACE
COMP1 E2 Low
CHARGE PUMP
PLL INHIBITION
VCO OSC
PHASE ADJUST
Figure 10 : Details of VCO
I0 2
I0
6.4V
RS FLIP FLOP
Loop Filter 7 4 I0
6
1.6V
(1.3V < V7 < 6V) R0 C0
10
6.4V 1.6V 0 0.875TH T
9110-27.EPS
The control voltage of the VCO is between 1.33V and 6V (see Figure 10). The theorical frequency range of this VCO is in the ratio of 1 to 4.5. The effective frequency range has to be smaller (1 to 4.2) due to clamp intervention on filter lowest value. In order to increase this effective frequency range, to a possiblerange of 1 to6.0 one canadda resistor from Pin 6 to Href leading. The synchro frequency must always be higher than the free running frequency. For example, when using a synchro range between 31kHz and 96kHz, the suggested free running frequency is 25kHz. The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage 2 which is I C adjustable between 2.65V and 3.75V (corresponding to 10%) (see Figure 11).
Figure 11 : PLL1 Timing Diagram
H Osc Sawtooth 7/8TH 1/8TH 6.4V 2.60V9110-28.EPS
Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.60V and 3.80V. The PLL1 ensures the exact coincidence between the signals phase REF and HSYNS. A T/10 phase adjustment is possible.
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TRAMEXT
I2C HPOS Adj.
TDA9110
OPERATING DESCRIPTION (continued) Figure 12 : LOCK/UNLOCK Block Diagram
5V
From Phase Comparator
NOR1
A
6V
The TDA9110 also includes a Lock/Unlock identification block which senses in real time whether the the PLL1 is locked or not on the incominghorizontal synchro signal. The resulting information is available on Hlockout (see Synchro Processor). The block function is described in Figure 12. The NOR1 gate receive the phase comparator output pulses (which also drive the charge pump). When the PLL1 is locked, we have on point A a very small negative pulse (about 100ns) at each horizontal cycle, so after the RC filter, there is a high level on Pin 14 which forces Hlockout to high level. The hysterisis comparator detects locking when Pin 14 reachs 6.5V and unlocking when Pin 14 decreases to 6.0V. When the PLL1 is unlocked, the 100ns negative pulse on Abecomes much larger and consequently the average level on Pin 14 decreases. It forces Hlockout to low level. The Pin 14 status is approximately the following : - near 0V when there is no H-Sync - between 0 and 4V with H-Sync frequency different from VCO - between 4 to 8 V when VCO frequency reaches H-Sync one (but not already in phase) - near 8V when PLL1 is locked. It is important to notice that Pin 14 is not an output pin but is only used for filtering purpose (see Figure 12). The lock/unlock information is also available through the I2C read. II.3 - PLL2 The PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO (Figure 13). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output current : 0.5mA). The flyback input consists of an NPN transistor. This input must be current driven. The maximum
recommanded input current is 5mA (see Figure 14). The duty cycle is adjustable through I2C from 30% to 60%. For Start Up safe operation, the initial duty cycle (afterPower on reset) is 60% in order to avoid to have a too long conduction of the BU transistor. Themaximumstoragetime isabout38% (TFLY/2.TH). Typically, TFLY/TH is around 20% which means that Ts max is around 28%. Figure 13 : PLL2 Timing Diagram
H Osc Sawtooth 7/8TH 1/8TH 6.4V 3.7V 1.6V
Flyback Internally Shaped Flyback H Drive Ts Duty Cycle
The duty cycle of H-drive is adjustable between 30% and 60%.
9110-30.EPS 9110-31.EPS
Figure 14 : Flyback Input Electrical Diagram
400
HFLY 12
Q1 20k
GND 0V
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20k H-Lock CAP 8 6.5V 220nF
B
3 HLOCKOUT
TDA9110
OPERATING DESCRIPTION (continued) II.4 - Output Section The H-drive signal is sent to the output through a shaping block ensuring Ts and H-drive duty cycle (I2C adjustable) (see Figure 13). In order to secure the scanning power part operation, the output is inhibited in the following cases : - when VCC is too low, - when the Xray protection is activated, - during the Horizontal flyback, - when the HDrive I2C bit control is off. The output stage consists of a NPN bipolar transistor. Only the collector is accessible(see Figure 15). Figure 15
VCC
Obviously the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be added between the circuit and the power transistor either of bipolar or of MOS type. II.5 - X-RAY Protection The X-Ray protection is activated by application of a high level on the X-Ray input (8V on Pin 25). The consequencies of X-Ray protection are : - inhibition of H-Drive output - activation of vertical blanking output. This protection is reset either by VCC switch off or by I2C (see Figure 16). II.6 - Horizontal and Vertical Dynamic Focus The TDA9110 delivers a horizontalparabola which is added on a vertical parabola waveform on Pin 15. This horizontal parabola comes from a sawtooth. The phase advance versus Horizontal flyback middle is kept constant for each frequency (about 860ns). This sawtooth is present on Pin 16 where the horizontal focus capacitor is the same as C0 to obtain a controlled amplitude (from 2 to 4.7V typically). Symmetry (keystone) and amplitude areI 2C adjustable (see Figure 17). The Vertical dynamic focus is tracked with VPOSand VAMP.Its amplitudecan be adjusted. It is also affected by S and C corrections. This positive signal has to be connectedto the CRT focusing grids.
26 H-DRIVE
The output NPN is in off-state when the power scanning transistor is also in off-state. The maximum output current is 30mA, and the corresponding voltage drop of the output VCEsat is 0.4V typically. Figure 16 : Safety Functions Block Diagram
VCC Checking VCC Ref
9110-32.EPS
I2C Drive on/off HORIZONTAL OUTPUT INHIBITION I2C Ramp on/off VERTICAL OUTPUT INHIBITION
9110-33.EPS
XRAY Protection XRAY VCC off or I2C Reset S R Q
Horizontal Flyback 0.7V
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TDA9110
OPERATING DESCRIPTION (continued) Figure 17
Horizontal Flyback
860ns
Internal Trigged Horizontal Flyback Horizontal Focus Cap Sawtooth
4.7V 2V 400ns
9110-34.EPS
Horizontal Dynamic Focus Parabola Output
Moire Output
2V
II.7 - Moire Output The moire output is intented to correct a beat between the horizontal video pixel period and the current CRT pixel width. The moire signal is a combination of the Horizontal and the Vertical frequency signals. To achieve a moire cancellation, the moire output has to be connected to any point of the chassis controlling the horizontal position. We recommend to introduce this " Horizontal Controlled Jitter" on the relative ground of PLL2 capacitor where this "controlled jitter" frequency type will directly affect the horizontal position. The amplitude of the signal is I2C adjustable. If the H-Moire feature is not necessary in the application, the H-Moire output (Pin 3) can be used as a 5 bits DAC output (0.3V to 2.2V). If the H-Moire output is not used at all, so the Pin 3 must be either kept to high impedance or grounded via a resistor.
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TDA9110
OPERATING DESCRIPTION (continued) III - VERTICAL PART III.1 - Geometric Corrections The principle is represented on Figure 20. Starting from the vertical ramp, a parabola shaped current is generated for E/W correction, dynamic horizontal phase control correction, and vertical dynamic Focus correction. The parabola generator is made by an analog multiplier, the output current of which is equal to : I = k (VOUT - VDCOUT)2 where Vout is the vertical output ramp (typically between 2 and 5V) and Vdcout is the vertical DC output adjustable in the range 3.2V to 3.8V which generate a dissymetric parabola if needed (keystone adjustment). In order to keep a good screen geometry for any end user preferencesadjustment,we implemented the "geometry tracking". Due to large output stages voltage range (E/W, FOCUS), the combination of tracking function with maximum vertical amplitude max or min vertical position and maximum gain on the DAC control may lead to the output stages saturation. This must Figure 20 : Geometric Corrections Principle
AMP 2 VDCOUT Internal Vertical Dynamic Focus added to Horizontal one EW amp VDCIN EW Output
be avoided by limiting the output voltage with apropriate I2C registers values. For the E/Wpart and the Dynamic Horizontalphase control part, a sawtooth shaped differential current in the following form is generated: I' = k' (VOUT - VDCOUT) Then I and I' are addedand converted into voltage for the E/W part. Each of the two E/W components or the two Dynamic Horizontal phase control ones may be inhibited by their own I2C select bit. The E/W parabola is available on Pin 24 via an emitter follower which has to be biased by an external resistor (10k). It can be DC coupled with external circuitry. The Vertical Dynamic Focus is combined with the Horizontal one on Pin 15. The dynamic Horizontalphasecontrol current drives internally the H-position, moving the Hfly position on the Horizontal sawtooth in the range of 1.4% TH both on SidePin Balance and Parallelogram.
Vertical Ramp V OUT
Keystone
Sidepin amp VDCOUT
To Horizontal Phase Sidepin Balance Output Current
Parallelogram 21/29
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TDA9110
OPERATING DESCRIPTION (continued) Figure 21 : Vertical Part Block Diagram
CHARGE CURRENT TRANSCONDUCTANCE AMPLIFIER REF 22 20 DISCH. OSC CAP SAMPLING SAMP. CAP S CORRECTION VS_AMP SUB07/6bits POLARITY COR_C SUB08/6bits C CORRECTION Vlow
Sawth. Disch.
V_SYNC 2
SYNCHRO
OSCILLATOR
23 VERT_OUT 18 BREATH
PARABOLA GENERATOR
24 EW_OUT
VERT_AMP SUB05/7bits VMOIRE SUB0C/5bits
EW_CENT EW_AMP SUB0A/6bits SUB09/7bits
VPOSITION SUB06/7bits
SPB_OUT
Internal Signal to PLL2 PARAL SUB0E/6bits SPB_AMP SUB0D/6bits
V_FOCUS Internal Signal added to H_FOCUS
9110-38.EPS
AMP 6bits
III.2 - EW EWOUT = 2.5V + K1 (VOUT - VDCOUT)2 + K2 (VOUT - VDCOUT) K1 is adjustable by the EW amplitude I2C register K2 is adjustable by the Keystone I2C register III.3 - DC HSize Output Control A 7 bits D/A converter is available on Pin 28. The output is a NPN transistor emitter follower output with an internal 100mA current source from output to ground (max. sunk current). The Max. current the output is able to source is 2.5mA. The output level is between 0.5V to 4.5V. This DAC can be used to control the H-Size. III.4 - Dynamic Horizontal Phase Control 2 IOUT = K5 (VOUT - VDCOUT) + K6 (VOUT - VDCOUT) K5 is adjustable by the SidePin Balance I2C register
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K6 is adjustable by the Parallelogram I2C register III.5 - Function When the synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 106Hz. The typical free running frequency can be calculated by : 1 f0 (Hz) = 1.6 e-5 COSC A negative or positive TTL level pulse applied on Pin 2 (VSYNC)as well as a TTLcomposite synchro on Pin 1 can synchronize the ramp in the range [fmin , fmax]. This frequency range depends on the external capacitorconnectedon Pin 22.A capacitor in the range [150nF, 220nF] 5% is recommanded forapplicationin thefollowingrange: 50Hz to 120Hz.
TDA9110
OPERATING DESCRIPTION (continued) Typical maximum and minimum frequency, at 25oC and without any correction (S correction or C correction), can be calculated by : f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0 If S or C corrections are applied, these values are slighty affected. If a synchronization pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more constant. An internal correction is activated to adjust it in less than a half a second : the highest voltage of the ramp Pin 22 is sampled on the sampling capacitor connected on Pin 20 at each clock pulse and a transconductanceamplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant. The read status register enables to have the vertical Lock-Unlock and the vertical Synchro Polarity informations. We recommand to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. A good stability of the internal closed loop is reached by a 470nF 5% capacitor value on Pin 20 (VAGC). III.6 - I2C Control Adjustments Then, S and C correction shapes can be added to this ramp. These frequence independent S and C corrections are generated internally. Their amplitudes are adjustable by their respective I2C register. They can also be inhibited by their Select bit. Finally, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on Pin 23 (VOUT) to drive an external power stage. The gain of this stage is typically 25% depending on its register value. The DC value of this ramp is driven by its own I2C r eg is t e r (ve rtic a l P o sit ion ). I ts v a lue is VCDOUT = 7/16 VREF 300mV. The VDCOUT voltage is correlated with DC value of VOUT. It increases the accuracy when temperature varies. By using the vertical moire, VDCOUT can be modulated from frame to frame. This function is intended to correct slightly the vertical video line to line period from actual CRT line to line width. III.7 - Basic Equations In first approximation,the amplitude of the ramp on Pin 23 (Vout) is : VOUT - VMID = (VOSC - VMID) (1 + 0.25 (VAMP)) with VMID = 7/16 VREF ; typically 3.5V, the middle value of the ramp on Pin 22 VOSC = V22 , ramp with fixed amplitude VAMP is -1 for minimum vertical amplitude register value and +1 for maximum On VDCOUT, the voltage (in volts) is calculated by : VDCOUT = VMID + 0.3 (VPOS) with VPOS equals -1 for minimum vertical position register value and +1 for maximum The current available on Pin 22 is : 3 IOSC = VREF COSC f
8
with COSC : capacitor connected on Pin 22 f : synchronization frequency
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TDA9110
INTERNAL SCHEMATICS Figure 22
5V 20k
Figure 23
5V
Pins 1 -2 H/HVIN VSYNC-IN
200
HMOIRE 3
9110-39.EPS
Figure 24
Figure 25
12V 5V HREF 13
PLL2C 4 HLOCKOUT
5
9110-41.EPS
Figure 26
12V HREF 13
Figure 27
12V HREF
13
C0
7
FC
6
9110-43.EPS
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TDA9110
INTERNAL SCHEMATICS (continued) Figure 28
HREF 13 12V HREF 13
PLL1F 9
Figure 29
R0 8
9110-45.EPS
Figure 30
12V
Figure 31
HREF 13 12V
HPOS 10
HFLY 12
9110-47.EPS
Figure 32
12V HREF 13
Figure 33
12V
HLOCKCAP 14
12V
HREF 13
HFOCUS 15
9110-49.EPS
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TDA9110
INTERNAL SCHEMATICS (continued) Figure 34
HREF 13 12V
Figure 35
12V
HFOCUS 16 CAP
BREATH 18
Figure 36
9110-51.EPS
Figure 37
12V
VCAP 22
12V
VAGCCAP 20
Figure 38
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Figure 39
12V
12V
EWOUT 24
VOUT 23
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TDA9110
INTERNAL SCHEMATICS (continued) Figure 40
12V
12V
Figure 41
HOUT 26
XRAY 25
9110-57.EPS
Figure 42
Figure 43
12V
12V
HSIZE 28
Pins 30-31 SDA - SCL
9110-59.EPS
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TDA9110
DEMONSTRATION BOARD
J16 1 J15 1 +5V J14 4 3 2 1
TP1 J11 HSYNC TP13 TP16 J12 +12V CC1 100nF +12V ICC1 - MC14528 CC4 1 TA1 47pF +12V 2 TA2 3 CDA 4 IA 5 IA 6 QA 7 QA 8 GND VCC 16 TB1 15 TB2 14 CDB 13 IB 12 IB 11 QB 10 100nF QB 9 C28 7 R35 10k R10 10k C25 33pF 820pF 5% R23 8 5.9k 1% C13 HOUT C22 33pF R8 10k 10nF 9 R0 C0 47pF R29 +12V 10 22nF C61 6 FC1 C7 5 CC3 PC1 47k CC2 10F VSYNC TP17 R28 3 10k 2 1
IC2 TDA9110
L1 10H H/HVIN +5V 32 C30 100F C32 100nF +5V
C39 22pF C40
R39 4.7k
R29 4.7k
R42 100 R41 100
22pF
VSYNCIN
SDA 31
PC2 47k
MOIRE
SCL 30
TP10
4
HLOCKOUT
VCC 29
+12V C6 100F C5 100nF R31 27k
E/W POWER STAGE
PLL2C
HSIZE 28 +12V +12V GND 27 R53 1k HOUT 26 C49 100nF XRAYIN 25 R7 10k 10F R45 33k TP14 R56 560 D2 C48 1N4148 R34 1k Q1 Q2 BC557 R37 27k R15 1k
R17 270k R19 270k C11 220pF R38 2.2 1W
J1 1 E/W
R33 4.7k
R9 470
R18 39k
Q3 TIP122
PLL1F
EWOUT 24
HOUT 1 J17
C31 R36 1.8k 4.7F 10 HPOS C62 1F C12 11 HGND C16 220pF 12 HFLY C27 47F C33 100nF HREF C15 13 HREF VA GCCAP 20 470nF C17 14 HLOCKCAP 220nF VGND 19 C2 100nF C3 47F 12k C41 470pF R5 5.6k R25 15 HVFOCUS 1k R24 10k DCBREATH 18 VREF 21 36k R2 5.6k R1 C4 7 100nF 1 2 6 IC1 TDA8172 4 3 5 R3 1.5 C1 220nF C8 100nF R11 220 1/2W R4 1 1/2W VCAP 22 150nF C18 100F 36V R40 TP7 VOUT 23
J8 1 HFLY
VERTICAL DEFLECTION STAGE
J2 1 D1 1N4004 C14 470F C9 +12V 100nF -12V TP8
1 J3
J18 1 2 3 V YOKE
C10 -12V 470F
J9 DYNAMIC FOCUS 1
+12V R73 1M R75 EHT 10k COMP R77 15k C60 100nF TP8 R74 10k
C34 820pF 5%
16 HFOCUSCAP
GND 17
P1 10k R76 47k
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TDA9110
PACKAGE MECHANICAL DATA 32 PINS - PLASTIC SHRINK DIP
Dimensions A A1 A2 B B1 C D E E1 e eA eB L
Min. 3.556 0.508 3.048 0.356 0.762 0.203 27.43 9.906 7.620
Millimeters Typ. 3.759 3.556 0.457 1.016 0.254 27.94 10.41 8.890 1.778 10.16 3.048
Max. 5.080 4.572 0.584 1.397 0.356 28.45 11.05 9.398
Min. 0.140 0.020 0.120 0.014 0.030 0.008 1.080 0.390 0.300
Inches Typ. 0.148 0.140 0.018 0.040 0.010 1.100 0.410 0.350 0.070 0.400 0.120
Max. 0.200 0.180 0.023 0.055 0.014 1.120 0.435 0.370
2.540
12.70 3.810
0.100
0.500 0.150
Information furni shed is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise und erany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1997 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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